VERIFICATION ENGINEER (3 – 5 YEARS)

Skills: UVM/OVM,Verilog
Job Locations: Delhi/NCR
Total vacancies: 3

• Must have experience in developing Verification environment from scratch
• Must be good in Verilog coding
• Must have Simulators experience using vcs/ncsim/modelsim
• Knowledge of  UVM/VMM methodology is desirable

To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to hr@incise.in with current CTC, expected CTC and notice period details. Our team will contact you for further details.