DVB Demod/Modulator

Two high-symbol-rate (HSR) demodulators:

• Maximum baud rate 500 Msymbol/s
• Up to two slices each
• DVB-S2/S2X and Annex M compliant
• Up to 8 multi-standard demodulators:
• S/S2/S2X/DTV
• Integrated full-band tuners and ADCs
• High-speed digital multiplexer to connect any tuner to any demodulator
• NCR PLL support

Flexible transport stream processor:

• PID filtering, PCR re-stamping and re-labelling, GSE label filtering
• TS merger (multiplex)
• Channel bonding
• Low power consumption
• Wake-on-network PID or GSE label
• Fast auto scan
• Signal monitoring, spectral analysis, bit error rate test and reporting

Interfaces:

• Crystal oscillator
• I2C serial bus interface, including private repeater for optional LNA
• TS, 8 serial, 2 parallel or multiplexed
• JTAG for boundary scan
• DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz
• FSK modem
• Flexible GPIOs and interrupts

Technology:

• Single rail supply with inbuilt SMPSs for internal supply generation
• Fine-grained power management
• VQFPN-mr 13×13 mm2 package, RoHS
• Temperature range -40 to +85 °C ambient

Applications

• Verilog Source RTL Code plus Simulation Environment
• Technical Documents

Deliverables

• Verilog Source RTL Code plus Simulation Environment
• C Source Code
• Physical Design scripts – Synopsys synthesis
• Hardware simulation test bench with regression test suit
• Reference platform drivers

• • Multi-core ARM® Cortex™ application CPU delivering up to 6000 DMIPS
  • High-performance GPU for fluid 3D graphics (ARM® Mali™-400)
  • DDR3/3L 32-bit interface running at up to 1066 MHz (DDR3-2133)
  • HEVC Main10 @ L4.1 (1080p60)
  • H.264 AVC, @ L4.2 (1080p60)
  • H.264 MVC and SHP @ L4.1 (1080p30L30R)
  • VC-1, MPEG4, MPEG2, AVS, AVS+
  • Web-based content decoding: Flash, DivX, Xvid, MJPEG, WMV
  • High-quality Faroudja video post-processing, including support for Blu-ray HDR10 content
  • HDMI-TX 1.4b/2.0a @ 1080p60 with HDCP 1.4 and 2.2
  • Supporting 802.11.a/b/g/n/ac wave 2
  • Up to 4 x 4 MIMO
  • Supports single-band 5 GHz or 2.4 GHz, or dual-band switchable
  • Generation 4 security for concurrent CA/DRM support, including schemes such as NSK 2.1, SVP, DTCP-IP, PlayReady, DVB-CPCM, DivX and Marlin
  • 1 x USB 2.0
  • 1 x USB 3.0
  • 1 x SD card
  • 1 x eMMC
  • 1 x Smartcard
  • 1 x Ethernet GMAC/RGMII
  • 4 x Input transport streams

Application

• • IP Client & Broadcast Platform – UHD 4Kp60
  • Server and Client Platform – UHD 60 fps
  • HEVC IP Client, Satellite or Cable Server – Dual HD/4K
  • Broadcast HD, HEVC, S2X/C/I

Deliverables

• Verilog Source RTL Code plus Simulation Environment
• C Source Code
• Physical Design scripts – Synopsys synthesis
• Hardware simulation test bench with regression test suit
• Reference platform drivers

• • DVB-T2 demodulation:
  • Compliant with ETSI EN-302755 v1.2.1
  • DTG7 v3 and Nordig Unified v2.4 compliant
  • 1.7, 5, 6, 7 and 8 MHz normal and extended BW signals supported
  • GS streams, FEF and MISO supported
  • DVB-T demodulation:
  • Compliant with ETSI EN-300744 v1.5.1
  • DTG7 v3 and Nordig Unified v2.4 compliant
  • 6, 7 and 8 MHz BW supported
  • DVB-C demodulation:
  • Compliant with ETSI EN300429
  • Nordig Unified v2.4 and SARFT compliant
  • Up to 7.2 Ms/s symbol rate
  • DVB-S and S2 demodulation:
  • Compliant with ETSI EN300421 and
  • EN302307
  • Symbol rates from 1 to 45 Ms/s
  • Enhanced FEC for DVB-S and DirecTV legacy transmissions
  • DVB-T/T2 and DVB-C compatible with zero-,high- and legacy-IF tuners (CAN or silicon)
  • DVB-S/S2 compatible with zero-IF tuners (CAN or silicon)
  • Embedded microcontroller (DVB-T2 task sequencing by firmware and monitoring)
  • ADC for RF signal strength indicator
  • Flexible clock management for advanced power saving
  • JTAG and I?C serial bus interfaces
  • I2C repeater for private tuner communications
  • Advanced low-power CMOS process
  • 3.3-V, 2.5-V and 1.1-V power supplies with internal SMPS for 1.1-V generation
  • Typical power consumption 912 mW (DVB-T2 mode)
  • TQFP80 10x10x1 mm3 package with EPD

Benefits

• • Error correction capabilities – Robustness
  • Error concealment capabilities – Quality
  • Compliance to Allegro reference streams

Deliverables

• Verilog Source RTL Code plus Simulation Environment
• C Source Code
• Physical Design scripts – Synopsys synthesis
• Hardware simulation test bench with regression test suit
• Reference platform drivers

• • Compliance with DVB-T2 standard
  • 1k, 2k, 4k, 6k, 16k, 32k FFT sizes.
  • 1/32, 1/16, 1/8,1/4, 1/128, 19/128, 19/256 Guard Intervals.
  • All Pilot Patterns PP1–?PP8.
  • By PLP code rates: 1/2, 3/5, 2/3,3/4 4/5, 5/6.
  • Constellations: QPSK, 16 QAM, 64 QAM, 256 QAM.
  • 16K and 64K LDPC
  • P1, P2, L1 and L2 reception and decoding.
  • Channel bandwidths: 1.7 MHz, 5MHz, 6 MHz, 7MHz, 8MHz
  • Output

Benefits

• • Silicon proven
  • Used in millions of devices

Deliverables

• Verilog Source RTL Code plus Simulation Environment
• C Source Code
• Physical Design scripts – Synopsys synthesis
• Hardware simulation test bench with regression test suit
• Reference platform drivers

Combined DVB-T/-C receiver

• • DVB-T demodulation
  • DVB-C demodulation
  • I²C serial bus interface
  • Compatible with low- to high-IF tuners
  • Flexible clock management
  • ADC for RF signal strength indicator
  • Flexible and DVB-CI compliant TS output
  • Ultra-compact TQFP64 package

Benefits

• • This highly integrated SoC helps to reduce board area and manufacturing cost, allowing low cost and small size STBs to be designed for either DVB-C or DVB-T networks.
  • Flexible AGC for different signal environments.
  • Best-in-class, low-power standby mode, to meet emerging energy standards for STBs.
  • Clock-rate management and improvements in channel acquisition efficiency enable a powerefficient standby mode.
  • Enables fast and seamless integration in complex digital TV systems such as iDTV, set-top boxes or PCTV dongles.

Deliverables

• Verilog Source RTL Code plus Simulation Environment
• Verification Environment
• Integration support
• Datasheet/Integration Guide/Verification Guide

• Tested in real broadcasting environment.
• KBS/MBC/SBS are using our equipment for field-measurement
• Conducted field test several times with MBC/SBS
• Conducted a plug-fest lead by government institution with KBS
• Well balanced S/W and H/W partitioning
• Easy to upgrade or add new feature
• Cortex M3 are sufficient to control
• Very highly optimized
• Fitted in single mid-sided FPGA(Virtex7 690T)
• Single port ram are mainly used for silicon area
• Ready to ASIC
• Not using any other IP
• Need only memory conversion to ASIC