IP/SOC DESIGN AND VERIFICATION
incise2025-01-14T10:16:47+00:00
INCISE FRONT END DESIGN EXPERTISE
IP Design
- Architecture, Specification and Micro-Architecture development
- Reusable RTL Design for Low Power, Minimum Area and Maximum Speed
- Synthesis, Timing Clean RTL, CDC, LINT
- Verilog, VHDL, System Verilog
SOC Design
- RTL Integration, 3rd Party IP Integration
- ARM, ARC, 8 Bit Processors, Starcore
- Timing constraints, Low power Clocking, Analog + Digital SOC
- FPGA to ASIC Migration, FPGA Prototyping & Validation
Projects Delivered
- UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform
INCISE IP/SOC VERIFICATION EXPERTISE
IP Verification
- System Verilog, UVM, OVM
- Specman, TCL, PERL
- Constrained Random TB
- Assertions, Functional Coverage, Code Coverage, Formal Verification
SOC Verification
- C++/C/Assembly Based Verification
- System Verilog, UVM, OVM
- Gate Level Verification
- System Level Verification/ FPGA Verification
- Coverage Driven
Projects Delivered
- UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform