Overview
The DVB-S2 is an FPGA-based waveform implementing a fully compliant DVB-S2
Transmitter and Receiver chain per ETSI EN 302 307-1. The VHDL IP core is
written in generic, synthesizable VHDL and is portable to any FPGA family. DVBS2X (ETSI EN 302 307-2) extensions are supported as a superset variant.
The transmitter and receiver designs are implemented on FPGA:
1. Transmitter (Tx) IP: MPEG Transport Stream (188-byte) or Generic Stream (GS) input → Input Stream Synchronizer & Null-Packet Deletion → CRC-8 (BB Header) → BB Scrambler (PRBS/LFSR) → BCH Outer Encoder → LDPC Inner Encoder (rates 1/4–9/10, normal 64800-bit / short 16200-bit frame) → Bit Interleaver → QPSK/8PSK/16APSK/32APSK Bit Mapper → PL Framing + Pilot Insertion → PL Scrambler → SRRC BB Filter
(α = 0.20/0.25/0.35) → IQ Modulation → RF/Satellite. Max payload: 858 Mbits/s (8PSK, rate 9/10, Kintex UltraScale+ -2).
2. Receiver (Rx) IP: ADC 16-bit IQ baseband input (sampling at 2×fclk_RXg) → DDC/NCO + AGC → SRRC Matched Filter (α = 0.20/0.25/0.35, user programmable) → PLFRAME Detection & Sync → PL Descrambler → Auto Symbol Demod (QPSK/8PSK/16APSK/32APSK — auto-detected per frame) → Bit De-Interleaver → LDPC Decoder (LLR-based iterative) → BCH Decoder → BB Descrambler → Null-Packet Re-insertion → Output TS/GS. Max payload: >675 Mbits/s (8PSK, rate 9/10, Kintex UltraScale+ -2). FEC frame type, modulation and encoding rate auto-detected on a frame-to-frame basis
Key Features of the System:
Transmitter (Tx) /Encoder & Modulator Chain:
• Flexible per-BBFRAME programmable attributes — frame length (16200/64800 bits), FEC encoding
rate and modulation type can change dynamically every BBFRAME for VCM/ACM operation
• Input stream flexibility — Single/Multiple MPEG Transport Streams (188-byte), Generic Stream
packetized or continuous, with input synchronizer, null-packet deletion and CRC-8 BB Header
encoding
• Concatenated FEC — BCH outer code (n_bch, k_bch) + LDPC inner code (n_dpc, k_dpc); 11 code
rates from 1/4 to 9/10; normal (64800-bit) and short (16200-bit) frame support
• QPSK/8PSK/16APSK/32APSK Gray-coded bit mapping with PLFRAME Header (MODCOD field)
signalling; dummy PLFRAME insertion for continuous output
• PL Scrambler (BLER), Pilot Insertion (P=36 pilots per 1476-symbol period), SRRC BB filter (α =
0.20/0.25/0.35) and quadrature modulation to 16-bit IQ DAC output
Applications:
• Secure Combat-Net Radio (CNR) — BPSK/QPSK for robust Low Probability of Intercept (LPI) / Low Probability of Detection (LPD) tactical links
• Wideband SIGINT / COMINT — real-time intercept, classification and replay of BPSK/QPSK/8PSK/OQPSK signals across L/S/CBand
• Airborne data-link for ALH-WSI / LCA Tejas — OQPSK for PAefficient links; QPSK/8PSK for Ku/Ka-band satellite feeder
• DVB-S2 BPSK/QPSK satellite ground segment (ISRO TTC & payload downlink)
• Missile & UAV telemetry downlink (C-Band) — QPSK/8PSK for high-rate sensor payload
• EW jamming assessment & ECCM trials — runtime PSK mode switching under Register MAP control
